MS9404M3 DP 1.4a Hub IC
The MacroSilicon MS9404M3 is a DP 1.4a Hub IC supporting one DP 1.4a input, two DP 1.4a outputs, and two HD 2.0 outputs. It integrates DP transceiver blocks, DSC decompression, CSC format conversion, video encryption/decryption, and an embedded MCU.
It supports up to three output ports for display expansion. The DP path supports up to 7680 x 4320 @ 60 Hz with DSC compressed output; the HD path supports up to 3840 x 2160 @ 60 Hz.
Key Specifications
| Item | Specification |
|---|---|
| Product type | DP 1.4a Hub (1 DP in, 2 DP out + 2 HD out) |
| DP RX | 1x DP 1.4a; 1/2/4 Lane; SSC |
| DP link rate | RBR 1.62 Gbps, HBR 2.7 Gbps, HBR2 5.4 Gbps, HBR3 8.1 Gbps |
| DP TX | 2x DP 1.4a; 1/2/4 Lane; static HDR |
| DP max output | 7680 x 4320 @ 60 Hz (DSC); 1–3 MST audio/video streams |
| HD TX | 2x HD 2.0, HD 1.x compatible; up to 6 Gbps |
| HD max output | 3840 x 2160 @ 60 Hz; DVI 1.0 support |
| Color depth / formats | RGB 6/8/10/12 bpc; YCbCr444/422/420 8/10/12 bpc |
| DSC | 1/2 Slice DSC decompression and DSC pass-through |
| HDCP | HDCP 1.x / 2.x encrypt/decrypt; HDCP Repeater |
| FEC | FEC encode/decode |
| Transport | SST; MST (1–3 streams) |
| MCU | Integrated 8051 core |
| Clock | Built-in POR; external 27 MHz crystal |
| Package | BGA224 (10 mm x 10 mm x 0.65 mm) |
Block Diagram
The block diagram shows DP RX/TX, HD TX, DSC/CSC, HDCP, and MCU connectivity inside MS9404M3.
Key Features
- Expands one DP 1.4a input to multiple DP and HD outputs for multi-display and heterogeneous output.
- Supports 8K DSC and 4K HD 2.0 output for high-resolution commercial AV.
- Integrated DSC decompression and CSC for format conversion across display interfaces.
- HDCP Repeater capability for protected content distribution.
- Embedded MCU for firmware customization and system control.
Typical Applications
- DP 1.4a multi-display docks and hubs
- Notebook DP to multi DP/HD output solutions
- Multi-screen heterogeneous output in commercial display and conferencing
- Professional video devices requiring DSC and HDCP 2.x
Design Notes
- Validate DP MST and HD output combinations with target OS and display capabilities.
- HDCP Repeater, FEC, and DSC configuration depend on MCU firmware; use vendor SDK and reference design for production.
- Plan PCB routing, thermal design, and 27 MHz clock carefully for BGA224.
- Refer to the official datasheet for pinout and registers.
References
Notes
This page is based on the official MacroSilicon product page. Confirm parameter limits, firmware capabilities, and production support with the latest datasheet and project validation.