MS9344 HD 2.0 Quad Splitter IC
The MacroSilicon MS9344 is an HD 2.0 splitter IC supporting one HD 2.0 input and four HD 2.0 outputs. It integrates color space conversion (CSC), video down-sampling, and other video processing blocks. Each port supports HDCP 1.4 and HDCP 2.3 video encryption and decryption. The chip embeds an 8051 MCU, supports external SPI Flash, and provides multiple user-configurable GPIO pins.
Key Specifications
| Item | Specification |
|---|---|
| Product type | HD 2.0 quad splitter (1 in, 4 out) |
| HD RX | 1 channel, HD 2.0 compliant, HD 1.x compatible |
| HD TX | 4 channels, HD 2.0 compliant, HD 1.x compatible |
| Maximum link rate | 6 Gbps |
| Maximum resolution | 4096 x 2160 @ 60 Hz (input/output) |
| Color depth / formats | RGB, YCbCr422, YCbCr444, YCbCr420; 8/10/12/16 bpc |
| Colorimetry | sRGB, BT601, BT709, BT1120, xvYCC601/709, sYCC601, Adobe RGB/YCC601, BT2020, etc. |
| HDR / 3D | HDR10 and 3D video input/output |
| HDCP | HDCP 1.4 / HDCP 2.3 encrypt/decrypt |
| Audio | 32 kHz–192 kHz PCM; DTS, Dolby, etc.; HBR Audio |
| Control / extension | CEC, SCDC; 5 V DDC compatible; 5 V HPD compatible input/output |
| Video processing | Color space conversion, video down-sampling |
| HD RX input | Descrambling, adaptive EQ |
| HD TX output | Scrambling, adjustable output drive |
| MCU | Integrated 8051 core; external SPI Flash; multiple user GPIO |
| Audio input | Single-channel input (CH0) |
| Clock / reset | Built-in power-on reset |
| Power | 3.3 V, 1.1 V, 2.5 V; integrated 3.3 V to 2.5 V LDO |
| Package | QFN-128 (12.3 mm x 12.3 mm) |
Block Diagram
The block diagram shows the relationship between HD RX, video processing, four HD TX paths, HDCP, MCU, and power management inside MS9344.
Key Features
- Distributes one HD 2.0 input to four HD 2.0 outputs, HD 1.x compatible.
- Per-port HDCP 1.4/2.3 encryption and decryption for protected content distribution.
- Integrated CSC and down-sampling for unified multi-output formatting.
- Supports HDR10, 3D, and high-bit-rate audio (HBR Audio).
- Integrated MCU and programmable GPIO for firmware customization and system control.
- Adaptive input EQ and adjustable output drive for long cables and multiple sinks.
Typical Applications
- HD 2.0 quad splitters and multi-display mirroring
- Professional AV distribution chassis with HDCP 2.3
- Multi-output HD systems in conference rooms, exhibitions, and control rooms
- Matrix/distribution sub-boards requiring MCU customization
Design Notes
- Compared with MS9334C (3 Gbps TMDS splitter), MS9344 targets HD 2.0 / 6 Gbps links; evaluate target resolution and HDCP version accordingly.
- Validate quad-output HDCP and EDID strategy at system level; MCU firmware and SPI Flash configuration require the vendor SDK.
- Plan 3.3 V / 1.1 V / 2.5 V power and thermal design for simultaneous four-output operation.
- Refer to the official datasheet for pinout, registers, and startup timing.
References
Notes
This page is based on the official MacroSilicon product page. Confirm parameter limits, MCU firmware capabilities, and production support with the latest datasheet and project validation.