A5001 4K UHD Decode SoC
A5001 is a 1.2 GHz HiChip A-series premium multimedia SoC with 128 MB integrated DDR3 SiP DRAM and H.264 @4K 30 fps decode. It provides HD output / VGA / CVBS display, HD input / CVBS video input, RMII Ethernet, and rich analog peripherals on RTOS in an eLQFP128 package.
The parameter library lists the same tier as A5000; the dedicated product page uses A5001. This page follows the product page.
Product Image
Key Specifications
| Item | Spec |
|---|---|
| CPU | 1.2 GHz |
| DRAM | 128 MB SiP @1600 Mbps (integrated DDR3) |
| Flash | SPI / NAND |
| Video decoder | H.264 @4K 30 fps |
| Display | HD output / VGA / CVBS |
| Video input | HD input / CVBS |
| Audio | I2S in + I2S out / 2ch PCM out / SPDIF out |
| USB | USB 2.0 ×2 |
| SDIO | SDIO 3.0 / eMMC 4.4 (4 line) |
| I2C/UART | 6×PWM, 2×I2C + 2×UART, IRRX, 4×TPADC, 1×SARADC |
| Ethernet | RMII |
| Wi-Fi | Support |
| SW system | RTOS |
| Package | eLQFP128 |
Typical Applications
- Network multimedia players
- Ultra-HD phone screen mirroring devices
- Gaming set-top boxes
- Home multimedia centers
- Karaoke audio systems
- HD interface buffers
Design Notes
- Integrated 128 MB DDR3 simplifies memory design for 4K decode and multi-display routing.
- The product page lists RTOS only (the parameter library sometimes shows Linux/RTOS); confirm OS/SDK support with the vendor if Linux is required.
- For 4K decode without HD video input, compare external-DRAM A5100.