CH582/CH583 BLE+USB MCU

CH582/CH583 are RISC-V BLE wireless MCUs from Nanjing Qinheng Microelectronics (WCH), integrating a Bluetooth Low Energy protocol stack and two independent USB 2.0 full-speed Host/Device controllers with PHY. Both offer 512 KB Flash, 32 KB SRAM, four UARTs, ADC, TouchKey, RTC, and related peripherals. CH583 adds SPI1 master mode and supports a lower minimum supply (1.7 V) versus CH582.

The series also includes CH581 (256 KB Flash, single USB, reduced peripherals). This page focuses on CH582/CH583.

Core Specifications

Item	Specification
Product type	RISC-V BLE wireless MCU (dual USB)
Core	QingKe RISC-V4A; RV32IMAC; hardware multiply/divide
Flash	512 KB FlashROM (448 KB CodeFlash + BootLoader + DataFlash partitions)
SRAM	32 KB (RAM30K / RAM2K retention regions)
Wireless	BLE; 2.4 GHz RF; 2M / 1M / 500k / 125k; -98 dBm RX sensitivity; programmable TX up to +6 dBm
USB	2× USB 2.0 full-speed Host/Device; 15 endpoints each; DMA; 64-byte packets; integrated PHY
Analog	14× 12-bit ADC + 2 internal channels; 14× TouchKey; on-chip temperature sensor
Interfaces	4× UART (up to ~6 Mbps); 2× SPI (CH583 includes SPI1 master); 1× I2C (SMBus)
Timers / PWM	4× 26-bit timers; 4× 26-bit PWM + 8× 8-bit PWM
GPIO	Up to 40 (20 on small packages); 32 interrupt/wake lines; some pins accept 5 V input
RTC	Timing and trigger modes
Security	AES-128; unique chip ID
Upgrade	ICP / ISP / IAP and OTA wireless update
Packages	QFN48 (5 mm × 5 mm), QFN28 (4 mm × 4 mm)

Part Differences (Selection Summary)

Part	Flash layout	BLE	USB	SPI	I2C	TouchKey	Min supply	GPIO	Package
CH583M	448+24+32K	Yes	2 Host + 2 Device	2 (incl. SPI1 master)	Yes	14 ch.	1.7 V	40	QFN48
CH582M	448+24+32K	Yes	2 Host + 2 Device	SPI0 master/slave	Yes	14 ch.	2.3 V	40	QFN48
CH582F	448+24+32K	Yes	2 Host + 2 Device	SPI0 master/slave	Yes	8 ch.	2.3 V	20	QFN28

Summarized from the CH583/CH582/CH581 datasheet. The CH583 product page lists BLE 5.3; some datasheet revisions reference BLE 5.0—confirm with your SDK/stack version.

CH582 vs CH583

• CH583: adds SPI1 master; CH583M minimum supply down to 1.7 V (also supports 1.8 V options).
• CH582: 2.3 V minimum; CH582M (QFN48) or CH582F (QFN28, fewer GPIO/TouchKey).
• Both integrate dual full-speed USB and a full BLE stack/API for USB + Bluetooth composite devices.

Block Diagram

Architecture of the Qingke RISC-V core, Flash/SRAM, BLE baseband/RF, dual USB, ADC/TouchKey, and peripherals (image source: openwch/ch583).

Key Features

• Single-chip BLE + dual USB without external USB PHY—suited to HID, CDC, MSD, composites, and BLE gateways.
• 512 KB Flash for stack and application code with OTA support.
• 14 ADC channels and TouchKey for sensors and low-power HMI.
• Integrated DC-DC and multiple sleep/shutdown tiers (sleep roughly 0.7–2.8 µA class per datasheet).

Typical Applications

• BLE transparent links, beacons, remotes, and IoT endpoints
• USB + Bluetooth dual-mode dongles, keyboards, mice, custom HID
• Dual-USB products (e.g., Type-A + Type-C composite functions)
• Battery-powered wearables/portables (CH583M low-voltage advantage)

Design Notes

• Supply: CH583M down to 1.7 V; CH582 requires 2.3 V minimum—match part and battery profile.
• Debug: SWD typically PB14/PB15; first WCH-Link use may require enabling 2-wire debug via WCHISPTool (hold Download entering BOOT).
• CH581: evaluate CH581 if single USB or 256 KB Flash is sufficient.
• Development: MounRiver Studio, openwch/ch583 SDK, and EVB materials.

References

• WCH CH583 product page (Chinese)
• WCH CH583 product page (English)
• CH583/CH582/CH581 datasheet PDF
• openwch/ch583 SDK and examples
• USB series
• Other model summary

Notes

This page is based on the WCH CH583 official product page and the public CH583/CH582/CH581 datasheet. Confirm part-specific differences, pinout, RF/USB coexistence, and production support with the latest vendor documentation, SDK, and project validation.