MS9601A HD 3x1 Switch IC
The MacroSilicon MS9601A is an HD 3-in, 1-out switch IC with a maximum signaling rate of 3 Gbps. At 3 Gbps, it supports HD input formats up to 4K @ 30 Hz.
The chip integrates DDC and HPD switchers that change together with the corresponding TMDS channels. Two embedded voltage regulators (5 V to 3.3 V and 1.8 V) simplify external power circuitry. It supports either an internal MCU with ROM code or external I²C control, and provides six selectable chip addresses for cascading. Adjustable input equalization and output drive levels accommodate different cable conditions. IR remote and key-based channel switching are also supported.
Key Specifications
| Item | Specification |
|---|---|
| Product type | HD 3x1 switch |
| Maximum data rate | 3 Gbps |
| Video interfaces | 3x HD inputs, 1x HD output |
| Maximum resolution | 4K @ 30 Hz |
| DDC / HPD | Integrated DDC/HPD switching synchronized with TMDS |
| Coupling | DC and AC coupling on inputs and outputs |
| Termination | Integrated input and output terminations |
| Signal conditioning | Adjustable input EQ; adjustable output drive level |
| Control | Internal MCU with ROM code or external I²C control |
| Cascading | Six selectable chip addresses |
| User interface | IR remote and key switching |
| Power | Embedded 5 V to 3.3 V and 1.8 V regulators |
| Package | LQFP-64 (10 mm x 10 mm) |
| Environmental | Pb-free, RoHS compliant |
Block Diagram
The block diagram shows multi-input HD switching, DDC/HPD routing, EQ/drive, embedded power, and control interfaces inside MS9601A.
Key Features
- Switches three HD inputs to one output for multi-source display applications.
- DDC/HPD routes with video channels for EDID and hot-plug management.
- Embedded power conversion reduces BOM and PCB area.
- Supports I²C control, IR, and keys for flexible UI integration.
- Six configurable addresses for cascaded matrix designs.
Typical Applications
- HD 3x1 switchers and matrix front ends
- Multi-source switching in conference rooms and classrooms
- Multi-input selection in security monitoring
- Cascaded HD switching chassis
Design Notes
- Plan I²C addresses and DDC/HPD timing carefully in cascaded designs to avoid bus conflicts.
- Validate signal margin on long inputs with EQ tuning.
- Refer to the official datasheet for pinout, registers, and default EDID strategy.
References
Notes
This page is based on the official MacroSilicon product page. Confirm parameter limits and production support with the latest datasheet and project validation.